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Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 13
UG230 (v1.2) January 20, 2011
Design Trade-Offs
R
Design Trade-Offs
A few system-level design trade-offs were required in order to provide the Spartan-3E
Starter Kit board with the most functionality.
Configuration Methods Galore!
A typical FPGA application uses a single non-volatile memory to store configuration
images. To demonstrate new Spartan-3E FPGA capabilities, the starter kit board has three
different configuration memory sources that all need to function well together. The extra
configuration functions make the starter kit board more complex than typical Spartan-3E
FPGA applications.
The starter kit board also includes an on-board USB-based JTAG programming interface.
The on-chip circuitry simplifies the device programming experience. In typical
applications, the JTAG programming hardware resides off-board or in a separate
programming module, such as the Xilinx Platform USB cable.
Voltages for all Applications
The Spartan-3E Starter Kit board showcases a triple-output regulator developed by Texas
Instruments, the TPS75003
specifically to power Spartan-3 and Spartan-3E FPGAs. This
regulator is sufficient for most stand-alone FPGA applications. However, the starter kit
board includes DDR SDRAM, which requires its own high-current supply. Similarly, the
USB-based JTAG download solution requires a separate 1.8V supply.
Related Resources
• Xilinx MicroBlaze Soft Processor
http://www.xilinx.com/microblaze
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• Xilinx Embedded Development Kit
http://www.xilinx.com/tools/platform.htm
• Xilinx software tutorials
http://www.xilinx.com/support/techsup/tutorials/
• Texas Instruments TPS75003
http://focus.ti.com/docs/prod/folders/print/tps75003.html
- Spartan-3E FPGA 1
- Starter Kit Board 1
- User Guide 1
- Revision History 2
- Table of Contents 3
- Chapter 6: VGA Display Port 5
- Chapter 12: SPI Serial Flash 6
- Chapter 13: DDR SDRAM 6
- Appendix A: Schematics 7
- About This Guide 9
- Additional Resources 10
- Introduction and Overview 11
- Key Components and Features 12
- Design Trade-Offs 13
- Switches, Buttons, and Knob 15
- Push-Button Switches 16
- Rotary Push-Button Switch 17
- Rotary Shaft Encoder 18
- Discrete LEDs 19
- Clock Sources 21
- ±2500 Hz or ±50 ppm 22
- Chapter 3: Clock Sources 24
- FPGA Configuration Options 25
- UG230_c4_01_022006 26
- Configuration Mode Jumpers 27
- PROG Push Button 28
- DONE Pin LED 28
- Connecting the USB Cable 29
- UG230_c4_06_022406 30
- UG230_c4_07_022406 30
- UG230_c4_08_022406 31
- UG230_c4_09_022406 31
- UG230_c4_10_022406 32
- UG230_c4_11_022706 33
- UG230_c4_12_022706 33
- Generating the PROM File 34
- UG230_c4_13_022706 34
- UG230_c4_14_022706 34
- UG230_c4_15_022706 35
- UG230_c4_16_022706 35
- UG230_c4_17_022706 36
- UG230_c4_18_022706 36
- UG230_c4_19_022706 37
- UG230_c4_20_022706 37
- UG230_c4_21_022706 38
- UG230_c4_22_022706 38
- UG230_c4_23_022706 39
- UG230_c4_24_022806 39
- UG230_c4_25_022806 40
- UG230_c4_26_022806 40
- UG230_c4_27_022806 41
- Character LCD Screen 43
- Voltage Compatibility 44
- LCD Controller 45
- UG230_c5_02_030306 47
- Command Set 48
- Disabled 49
- Clear Display 49
- Return Cursor Home 49
- Entry Mode Set 49
- Display On/Off 50
- Cursor and Display Shift 50
- Function Set 51
- Set CG RAM Address 51
- Set DD RAM Address 51
- Read Busy Flag and Address 51
- Operation 52
- Power-On Initialization 53
- Display Configuration 53
- VGA Display Port 55
- UG230_c6_02_021706 57
- VGA Signal Timing 58
- Chapter 6: VGA Display Port 60
- RS-232 Serial Ports 61
- PS/2 Mouse/Keyboard Port 63
- Keyboard 64
- UG230_c8_03_021806 65
- UG230_c8_04_021806 66
- UG230_c8_05_021806 66
- Voltage Supply 67
- Chapter 9 69
- Interface Signals 70
- SPI Communication Details 71
- Communication Protocol 71
- DAC Outputs A and B 72
- DAC Outputs C and D 72
- Analog Capture Circuit 75
- UG230_c10_02_022306 76
- Programmable Pre-Amplifier 77
- SPI Control Interface 78
- Interface 79
- Connecting Analog Inputs 81
- Chapter 11 83
- StrataFlash Connections 84
- Shared Connections 87
- SPI Serial Flash 91
- Configuring from SPI Flash 92
- UG230_c15_04_030206 93
- UG230_c15_05_030206 94
- UG230_c15_06_030206 94
- UG230_c15_07_030206 95
- UG230_c15_08_030206 95
- UG230_c15_09_030206 96
- UG230_c15_10_030206 96
- UG230_c15_11_030206 96
- UG230_c15_12_030206 97
- UG230_c15_13_030206 97
- Downloading the SPI Flash 98
- with Flying Leads 99
- Additional Design Details 100
- °. The 16-pin SOIC 101
- (Do not connect) 102
- UG230_c15_18_030606 102
- Related Resources 103
- Chapter 12: SPI Serial Flash 104
- DDR SDRAM 105
- DDR SDRAM Connections 106
- UCF Location Constraints 108
- Chapter 13: DDR SDRAM 110
- 25 MHz Crystal 111
- UG230_c14_01_022706 111
- Ethernet PHY Connections 112
- UG230_c14_03_022706 113
- Expansion Connectors 115
- Hirose 100-pin Expansion 116
- Connector (J3) 116
- Compatible Board 118
- Mating Receptacle Connectors 118
- Differential I/O 118
- Using Differential Inputs 120
- Using Differential Outputs 121
- UG230_c12_05_022406 121
- UG230_c12_06_022406 121
- Six-Pin Accessory Headers 123
- XC2C64A CoolRunner-II CPLD 127
- UG230_c16_01_030906 128
- UG230_c17_01_030906 131
- Schematics 133
- UG230_Aa_01_021806 135
- UG230_Aa_02_021806 137
- Appendix A: Schematics 138
- UG230_Aa_03_021806 139
- Voltage Regulators 140
- UG230_Aa_04_021806 141
- Flash, JTAG Connections 142
- UG230_Aa_05_021806 143
- UG230_Aa_06_021806 145
- FPGA I/O Banks 2 and 3 146
- UG230_Aa_07_021806 147
- Power Supply Decoupling 148
- UG230_Aa_08_021806 149
- UG230_Aa_09_021806 151
- UG230_Aa_10_021806 153
- UG230_Aa_11_021806 155
- UG230_Aa_12_021806 157
- Termination 158
- UG230_Aa_13_021806 159
- Appendix B 161
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